A Constraint Logic Programming Based Approach to High-Level Synthesis for Low Power

This paper presents high-level synthesis problems and solutions specific for low power synthesis. It includes ideas of how to minimize the power consumption by switched capacitance reduction during operation scheduling and resource binding. This process uses switching activity data obtained from simulation of the design at the register transfer level. The novelty of this approach is the use of constraint logic programming which enables minimization of the switching activity while performing scheduling and binding in one synthesis step. Preliminary experimental results confirm the importance and the feasibility of the method described here.